Ser. No. 09/507,645, filing date Feb. 22, 2000, xe2x80x9cA NEW HARD MASK PROCESS FOR SALICIDE GATE WITH A SPECIAL ETCHxe2x80x9d, C. H. Yu and S. M. Jang, assigned to a common assignee.
(1) Field of the Invention
The invention relates to processes for the manufacture of semiconductor devices and more particularly to processes for forming suicides on self-aligned polysilicon gate field effect transistors.
(2) Background of the Invention and Description of Previous Art
Self-aligned polysilicon gate field effect transistors are widely used as the preferred semiconductor device in nearly all integrated circuit applications. This is because of their low current utilization and ease of manufacture compared to bipolar transistors. In addition, the simple structure of these devices lends itself well to size reduction, thereby permitting many thousands of complex circuits to be fabricated on a relatively small chip area. One outstanding characteristic of these devices is the ability to ability to form their source and drain device elements self-aligned to the polysilicon control gate. In recent years the electrical performance of these devices has been further improved by including a LDD (lightly doped drain) structure which is also formed, self-aligned to the control gate.
For many years the FET (field effect transistors) device was fabricated in active silicon island surrounded by a field oxide which was formed by the LOCOS (local oxidation of silicon) process. The LOCOS process was first proposed by Kooi in the mid 1960""s and has enjoyed a long period of success. However, in recent years, many applications are replacing LOCOS field oxide with shallow trench isolation (STI) which can be adapted to smaller dimensions and is exempt form the traditional LOCOS problems such as xe2x80x9cbirds beakxe2x80x9d and thermal stresses. STI is formed by anisotropically etching trenches into the silicon substrate, providing a thin thermal oxide liner, and then filling the trenches with an insulative material at low temperatures. Typically, silicon oxide is deposited into the openings at low temperatures by PECVD (plasma enhanced chemical vapor deposition). The surface is then planarized by CMP (chemical mechanical polishing).
FIG. 1 shows a cross section of a familiar form of the self-aligned polysilicon gate MOSFET (metal oxide silicon field effect transistor) 8. formed with STI. The silicon oxide filled trenches 24 form the field isolation around the device 8. The polysilicon gate electrode 16 is photolithographically patterned over a thin gate oxide 14 using photoresist. The LDD portions 18 of the source/drain elements are then formed by ion implantation using the gate 16 as a self-aligned mask. Sidewall spacers 20 are formed which then, along with the gate electrode 16 mask the main portions 22 of the source/drain elements in a second ion implantation. A refractory metal, for example titanium, is deposited over the wafer and is reacted with the polysilicon gate and the exposed source/drain region to form TiSi2. Unreacted Ti is removed by wet etching leaving the TiSi2 26 on the silicon surfaces. Formation of a silicide simultaneously on the polysilicon gate and source drain regions to form contact regions is known as the salicide (self-aligned silicide) process.
In earlier technologies, relatively thick photoresist masks were allowable to protect the polysilicon during patterning of the gate electrode 16 by anisotropic etching. Present day sub-quarter micron technology, no longer permits the use of thick photoresist layers because of the reduced depth of field at the shorter radiation wavelengths used to expose the patterns. It therefore becomes expedient to introduce a hard mask for patterning the polysilicon gate 16. The use of a hardmask also provides higher etch rate selectivities between polysilicon and silicon oxide, thereby improving the capability of stopping the etch on the thin gate oxide layer. The hardmask material is first deposited over the polysilicon layer and patterned with a thin photoresist mask. The hardmask material, typically silicon oxide, is more durable in the polysilicon gate patterning plasma than photoresist.
Lee, U.S. Pat. No. 5,431,770 teaches the use of a hardmask, typically SiO2, which is patterned by photoresist and then isotropically wet etched to reduce it""s planar dimensions below the dimensional limits of the photolithography. The shrunken mask is then used to etch device features which are smaller than the photolithographic limits. Similarly, Roth. et.al., U.S. Pat. No. 5,061,647 anisotropically etches a pattern in a conductive layer with a photoresist mask and then undercuts the photoresist by isotropically etching the conductive layer to laterally and uniformly reduce it""s lateral dimensions below the photoresist dimensions. The reduced conductive layer pattern is then used as a hardmask to anisotropically etch features in subjacent layers which are smaller than the original photolithographic pattern.
Hsu, et.al., U.S. Pat. No. 5,796,151 teaches a Si3N4 layer covering a partially formed gate stack having W and TiN layers. The Si3N4 layer forms a sidewall on the partially formed gate stack and serves as a hardmask for further etching the gate stack through a polysilicon layer stopping in a gate oxide. Alternately silicon oxynitride or silicon oxide may be used in place of the Si3N4. Langley, et.al., U.S. Pat. No. 5,169,487 etches a silicon oxide, silicide, polysilicon stack stopping in a subjacent silicon oxide layer using a photoresist mask which survives the entire etch process. Carbon generated by the etch gases and by erosion of the photoresist passivates the sidewalls of the structure thereby permitting an essentially vertical etch profile.
Referring again to FIG. 1, after the gate 16 is patterned a refractory metal silicide layer 26 is selectively formed on the polysilicon gate 16 and the active silicon regions 18, 22 which will form the source/drain elements of the FET. This process is also self-aligning and is commonly referred to as the xe2x80x9csalicidexe2x80x9d (self-aligned silicide) process. The silicide coating improves the conductivity of the polysilicon and assists in achieving good ohmic contact to the source/drain regions of the device. However, a problem has been found to occur by the present inventors, when a silicon oxide hardmask is used to pattern the polysilicon gate electrode when silicon oxide STI is present.
FIG. 2A shows a cross section of an in-process self-aligned polysilicon gate MOSFET after the polysilicon gate has been patterned with a silicon oxide hardmask 28. The anisotropic polysilicon etch is terminated on the gate oxide 14. Referring to FIG. 2B, the residual hardmask 28 as well as the thin gate oxide 14 over the active silicon regions adjacent to the gate structure 16 are removed after sidewall 20 formation, by wet etching with dilute HF to prepare the silicon surfaces for salicide formation. However, the wet etchant also attacks the exposed STI 24. This results in an unacceptable gouging 29 of the STI in the trenches. The gouging has been found by the present inventors to penetrate the STI sufficiently to interact with the adjacent source/drain junctions causing serious device degradation by junction leakage. Subsequently formed conductive silicide along the exposed walls of the trenches can cause junction leakages and shorts.
Field isolation formed by the LOCOS process does not present these problems. Junctions abutting LOCOS field isolation have sufficient thickness of overlying oxide at the point of abutment, that an HF etchant can safely be used to remove residual SOG or silicon oxide hardmask, without risking exposure of the junction. This margin of error is not available to STI isolation. It would therefore be desirable to have a hardmask material and an etchant-formulation which etches the hardmask much faster than silicon oxide so that the hardmask may be safely removed with minimal attack of the STI, This invention provides a formulation for such a hardmask and etchant as well as a method for use which provides additional benefits.
It is an object of this invention to provide an improved method for patterning a polysilicon gate electrode on a polysilicon gate MOSFET with shallow trench isolation.
It is another object of this invention to provide a hardmask for patterning polysilicon and polycide layers which has a high durability for plasma etching of polysilicon and in addition, has an etch rate in an aqueous HF etchant which is significantly greater than the etch rate of silicon oxide in the same aqueous HF etchant.
It is yet another object of this invention provide a hardmask which can be thermally flowed to improve the planarity of subsequently applied photoresist and thereby improve the overall sharpness of focus in narrow depth of field photolithography.
It is still another object of this invention to provide a method for forming a self-aligned polysilicon gate MOSFET with STI and with salicide contact metallization.
It is yet another object of this invention to provide a method for reducing gate-to-source/drain bridging in a polysilicon gate MOSFET.
These objects are accomplished by patterning the polysilicon layer with a hardmask formed of BPSG (borophosphosilicate glass) or PSG (phosphosilicate glass). BPSG and PSG offer the additional advantage of being thermally flowable to provide a planer surface. A silicon wafer having regions of shallow trench silicon oxide isolation is provided. A gate oxide is formed and a polysilicon layer is deposited on the gate oxide. A layer of the flowable hardmask material is then deposited on the polysilicon and the layer is thermally flowed which forms a more planar surface. The hardmask is prepared by first depositing an organic BARC (bottom anti-reflective coating) on the blanket layer of hardmask material. The hardmask is then patterned by using a photoresist mask. Residual photoresist is stripped and the polysilicon layer is anisotropically etched by RIE (reactive ion etching) or by plasma etching. The hardmask suffers little erosion during polysilicon etching which is conducted under conditions of high polysilicon-to-silicon oxide selectivity so that the etching may be safely terminated on the subjacent gate oxide. An over-etch period is provided to removed all vestiges of un-masked polysilicon without penetration of the gate oxide.
The residual hardmask is wet etched with the aqueous dilute HF just prior to source/drain ion implantation. Attack of exposed STI oxide by the HF etchant is negligible because the hardmask material etches much faster that the STI oxide. A layer of titanium is then deposited. A protective TiN layer may be alternatively be deposited over the Ti layer. A rapid thermal anneal forms TiSi2 in the regions where silicon and polysilicon surfaces are in contact with the Ti layer. Wet etching in NH4OH and H2O2, removes the TiN and unreacted Ti, leaving TiSi2 on the polysilicon patterns and on the silicon active areas. The sidewalls, having been formed with the residual hardmask in place, extend above the plane of the polysilicon gate. This provides an extended surface path between the gate and the source/drain regions and thereby reduces the risk of gate-to-source/drain bridging during silicide formation.